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And its foundry market share has been cut roughly in half.
This article goes deep on one specific question: why has Samsung's $200 billion failed to close the gap with TSMC? It assumes you already understand TSMC's core business how it makes money, who its customers are, and how node pricing works. If not, start there first.
TSMC spent $40.9B on capex in 2025 : this is why no competitor has caught up
The question nobody asks loudly enough
Samsung has spent more money trying to compete with TSMC than most countries spend on infrastructure in a decade. It has access to EUV lithography. It has world-class engineers. It has been manufacturing chips since 1974.
And its foundry market share has been cut roughly in half.
The standard explanations do not hold. Better technology? Samsung has world-class technology. More experience? Samsung has decades of chip manufacturing history. More capital? Samsung's semiconductor division has more capital than most companies on earth.
None of those explanations survive contact with the actual market share data. Something else is happening. Understanding what it is matters for anyone analyzing NVIDIA, Apple, AMD, or Qualcomm companies whose entire product roadmaps run on TSMC's manufacturing capability.
Capital is the entry fee, not the moat
TSMC's $40.9 billion in 2025 capex gets most of the coverage. It is genuinely large larger than AMD's entire annual revenue, and the largest single-year capital commitment in semiconductor history when you include the $52-56 billion 2026 guidance.
But capital is the cost of staying in the game. It is not the reason TSMC wins it.
ASML's High-NA EUV lithography machines cost approximately $380 million per unit. Any company with the money can buy them. Samsung buys them. Intel buys them. The machines are available to anyone who can afford them lead time from order to delivery is the main constraint, not access.
If capital and equipment were the moat, Samsung's $200 billion would have closed the gap.
It has done the opposite.
The foundry market is worth approximately $185 billion today and is expected to reach $360 billion by 2036 a near doubling in a decade. TSMC's share of that market is not declining as the total grows. It is increasing. At advanced nodes specifically, TSMC's share is above 90%. The market is getting larger and TSMC is getting more dominant within it at the same time.
That does not happen when the moat is just capital.
Layer 1: the yield data advantage
Here is what genuinely cannot be purchased: manufacturing history.
TSMC has been running advanced node fabs since the early 2000s. Every production run generates data where defects appear, what process adjustments fix them, how specific chip architectures interact with the manufacturing environment at the nanometer scale. That data accumulates across thousands of runs and hundreds of billions of wafers. It is the foundation of yield rate improvement, and yield rate is the metric that determines whether a fab is profitable or a money pit.
When TSMC launches N2, it does not start with zero yield knowledge. It starts with 35 years of manufacturing runs that inform every process decision. The engineers setting up N2 learned on N3. The engineers who ran N3 learned on N5. The process knowledge is layered and cumulative in a way that cannot be replicated by buying equipment and hiring engineers, regardless of how much you spend.
A competitor launching an advanced node today has no yield history at that node. They spend years discovering defect mechanisms that TSMC already solved. During those years, TSMC's yields are better, its cost per good wafer is lower, and its customers are not waiting for the competitor to catch up.
N2 entered high-volume manufacturing in Q4 2025. Management described yields as "good" not adequate, not acceptable. From a company that uses language carefully on earnings calls, that specific word choice matters. N2 wafer capacity is ramping from approximately 50,000 wafers per month toward a target of 140,000 wafers per month in 2026. That ramp is happening because yields are sufficient to serve customers profitably, not because TSMC is forcing output regardless of quality.
Apple has reportedly secured over 50% of N2 capacity allocation. That allocation did not happen because Apple ran a competitive tender and TSMC won on price. It happened because Apple designed its next generation of chips around TSMC's N2 process specifications a design process that takes 3-5 years and requires deep technical collaboration between chip architects and foundry process engineers.
Layer 2: the co-development lock-in
TSMC does not just manufacture chips. It co-develops them.
Apple, NVIDIA, and AMD share their next-generation chip roadmaps with TSMC years before those chips reach production. The chip architects at these companies work directly with TSMC's process engineers to optimize designs for the manufacturing environment. TSMC's process parameters shape chip design decisions before a single transistor is laid out on silicon.
This creates a lock-in that is different in character from software switching costs. It is not that customers are reluctant to switch it is that switching requires rebuilding the entire chip design process around a different foundry's process parameters. Years of co-development, billions in R&D, and the accumulated expertise of hundreds of engineers is tuned to TSMC's specific manufacturing environment. Switching foundries is not a procurement negotiation. It is a multi-year engineering project that means rewriting chip architectures from the beginning.
Intel's foundry business has made genuine technical progress. The 18A process is competitive on paper. But Intel's foundry customers face a specific problem: Intel Foundry's process parameters are new. There is no co-development history. No accumulated knowledge of how specific customer chips interact with Intel's manufacturing environment at the nanometer scale. The technical merit of the process is real. The trust that comes from years of production runs and joint development is not yet there and in semiconductor manufacturing, trust is built through production history, not marketing presentations.
I think this is the layer that gets underestimated the most. The switching cost is not just financial. It is embedded in years of design decisions that cannot simply be reversed.
Layer 3: the talent and culture effect
This is the layer that gets the least coverage. It is probably the most durable.
TSMC recruits top engineering talent across Taiwan, Japan, India, and increasingly the United States. The company's culture intense, detail-oriented, manufacturing-focused filters for engineers who treat process perfection as something they care about personally, not a requirement they meet. In semiconductor manufacturing, the difference between a node that works and one that does not often comes down to individual engineers catching problems that no automated system flagged.
That culture does not ship with the equipment when TSMC builds fabs in Arizona. The Arizona fabs have required substantial workforce training precisely because the manufacturing culture that exists in TSMC's Taiwan facilities is built over years of organizational experience. It is not transferred along with the lithography machines.
This creates a paradox in the CHIPS Act story that most analysis misses. The billions the US government is investing to bring TSMC manufacturing to Arizona are largely funding TSMC's capacity expansion, not building a domestic alternative to it. Intel Foundry is struggling. Samsung's US foundry presence is limited. The CHIPS Act is funding TSMC's growth more than it is building competition for TSMC. Whether that is wrong as policy is a separate question having advanced chip manufacturing in the United States is valuable regardless of who operates it. But it does mean the competitive landscape in 2028 looks essentially the same as it does today.
Why 2026 is a critical year for the N2 ramp
N2's ramp from 50,000 to 140,000 wafers per month in 2026 is the most consequential capacity story in semiconductors right now.
N2 uses gate-all-around transistor architecture a fundamental shift from the FinFET structure used in N3 and all prior nodes. Gate-all-around improves power efficiency by roughly 25-30% versus N3E and is required for continued performance scaling at sub-2nm nodes. Every company building competitive AI accelerators, smartphones, or data center processors in 2027-2028 needs N2 or the A16 process that follows it. Which means they need TSMC.
N2 wafers are priced approximately 50% higher than equivalent N3 wafers. If the ramp to 140,000 monthly wafers materializes, it adds roughly $35-40 billion in annualized revenue potential from N2 alone before N3 volume, before N5, before anything else.
Apple's 50%+ capacity allocation at N2 means the second-largest customer revenue stream in TSMC's business is locked in at the new pricing tier before the node is fully ramped. That is pricing power operating ahead of supply, not alongside it.
ASML is the only company in the world that manufactures the EUV machines TSMC uses at leading nodes a monopoly within TSMC's monopoly. ASML's order books reflect TSMC's capacity expansion plans 12-18 months in advance. Each N2 fab configuration requires multiple EUV machines at approximately $380 million each. The equipment manufacturers ASML, Applied Materials, Lam Research, KLA see the TSMC capacity expansion in their order books well before TSMC sees it in revenue.
What this means for NVIDIA and AMD investors
NVIDIA's business $215.9 billion in revenue, 71% gross margin, zero factories -- is entirely dependent on TSMC's manufacturing capability and capacity allocation decisions.
When NVIDIA announces a new GPU architecture, the question that follows immediately is not "how powerful is it" but "can TSMC make enough of them, and when." Blackwell's ramp into volume production was gated by TSMC's N4/N5 capacity. Vera Rubin the next NVIDIA architecture -- will be gated by N2 capacity.
This creates a specific dynamic worth understanding: NVIDIA can design the best chip in the world, but the rate at which it reaches customers is determined by TSMC's fab capacity and yield rates, not NVIDIA's engineering team. When C.C. Wei describes N2 yields as "good," he is simultaneously providing NVIDIA's supply chain a forward production signal.
AMD is in an identical position. Every Instinct MI series data center GPU and every EPYC server processor runs on TSMC advanced nodes. AMD's market share gains against Intel in server CPUs over the last four years are partly a TSMC story TSMC's N5 and N7 process advantage over Intel's own manufacturing gave AMD a process lead that translated directly into performance and power efficiency advantages at the product level.
For the full breakdown of how NVIDIA's fabless model and TSMC dependency works in practice:
NVIDIA made $215.9B without owning a factory : the business model behind the number
The one risk that could change the analysis
Everything above is an argument that TSMC's competitive position strengthens over time. That may be true. But one scenario changes the analysis.
If AI model training efficiency improves dramatically if the compute required per unit of AI capability falls faster than current projections hyperscaler GPU demand could normalize sooner than expected. TSMC's expansion plans are built on the assumption that demand for advanced node wafers grows at a rate justifying $52-56 billion in annual capex. If the AI efficiency curve steepens beyond what the semiconductor industry expects, the demand side of that equation changes.
This is not a prediction. It is a watch signal.
The specific indicator: compute efficiency per AI benchmark how many GPU-hours it takes to train a model of a given capability level. That metric has been improving. If it improves faster than the semiconductor industry is modeling, the capacity cycle TSMC is investing in may be sized for demand that materializes more slowly than planned.
For the full macro picture including hyperscaler capex sustainability:
TSMC earns 74% of revenue from the US : one tariff decision rewrites the investment case
The Samsung case study is the most analytically useful data point in semiconductors and the least discussed. A company with effectively unlimited capital, world-class engineers, and decades of chip manufacturing experience has been losing advanced foundry market share to TSMC for years. At leading nodes specifically, Samsung's share has been cut roughly in half over the last two years.
That result is not explicable by capital or technology alone.
I keep coming back to the yield data point. Samsung's engineers are not less capable than TSMC's. The equipment is comparable they both buy from ASML. The difference is that TSMC has been running the same learning cycle for 35 consecutive years: launch node, identify defects, optimize yield, accumulate data, apply to next node. Samsung has not. That gap does not close with a capital commitment. It closes with time, and time is the one thing money cannot compress in semiconductor manufacturing.
The CHIPS Act paradox reinforces this. The US government is spending billions to onshore advanced chip manufacturing, and the primary beneficiary is TSMC's capacity expansion not a domestic challenger. That is not a criticism of the policy. It is just the reality of where advanced manufacturing expertise actually lives in 2026.
The N2 ramp from 50,000 to 140,000 monthly wafers in 2026 is the specific data point to track not as a revenue forecast, but as a proof point for whether TSMC's manufacturing advantage extends cleanly to gate-all-around architecture.
If N2 reaches 140,000 monthly wafers by Q4 2026 with management describing yields as "good" or better in quarterly commentary, the moat extends to the next architecture generation as expected. TSMC's process development is compounding.
If N2 ramp encounters unexpected yield challenges not minor, but something management flags explicitly in earnings commentary that would be the first evidence since N7 that a technology transition meaningfully challenged TSMC's process execution. Worth paying close attention to if it happens.
Check TSMC's per-quarter N2 revenue contribution against the 50,000 to 140,000 wafer-per-month trajectory. That number tells you whether the advantage compounds or plateaus at gate-all-around.
FAQs
Why does TSMC dominate the semiconductor foundry market?
TSMC's competitive position rests on three things that cannot simply be purchased: accumulated yield data from 35+ years of manufacturing runs, customer co-development relationships where chip designers build their architectures around TSMC's process parameters over 3-5 year cycles, and a manufacturing culture tuned to process perfection at the organizational level. Capital and equipment are available to competitors. These three things are not or not quickly enough to matter.
Why hasn't Samsung been able to close the gap with TSMC?
Samsung invested approximately $200 billion in foundry operations over the last decade. Its market share dropped from 13% to roughly 7% over the same period. The gap persists because the moat is not capital it is accumulated manufacturing knowledge, yield data across thousands of production runs, and customer trust built through decades of co-development. Money cannot compress the time required to build those things.
What is the N2 node and why does the ramp matter?
N2 is TSMC's newest process, which entered high-volume manufacturing in Q4 2025. It uses gate-all-around transistor architecture a fundamental change from FinFET-based nodes and is priced approximately 50% higher per wafer than N3. The ramp from 50,000 to a targeted 140,000 monthly wafers in 2026 is the largest capacity expansion TSMC has attempted at a new node. Apple has reportedly secured 50%+ of initial N2 capacity. If yields hold at "good" levels through the ramp, N2 adds roughly $35-40 billion in annualized revenue potential.
Does TSMC's dominance create systemic risk?
Yes, and it is underappreciated in most public analysis. Taiwan produces approximately 92% of the world's advanced logic chips. TSMC produces the vast majority of that. A disruption to Taiwan's semiconductor manufacturing would affect every company dependent on advanced chips simultaneously. There is no near-term substitute. TSMC's Arizona, Japan, and Germany expansions reduce this risk over time but do not eliminate it in the 2026-2028 window.
What does TSMC's dominance mean for NVIDIA and AMD investors?
Both companies' product roadmaps are gated by TSMC's capacity and yield rates. NVIDIA's Vera Rubin architecture and AMD's next-generation data center products both depend on N2 availability. When TSMC's management signals strong yields and capacity expansion, it is simultaneously signaling that NVIDIA and AMD production can proceed on schedule. Monitoring TSMC's quarterly capacity commentary is a leading indicator for both companies' near-term supply chain visibility.
How does ASML fit into the TSMC picture?
ASML is the sole manufacturer of EUV lithography machines required for advanced node production a monopoly within TSMC's monopoly. ASML's order books reflect TSMC's capacity expansion plans 12-18 months in advance. Each N2 fab configuration requires multiple EUV machines at approximately $380 million each. ASML and TSMC are structurally linked: TSMC's growth requires ASML's equipment, and ASML's order flow reflects TSMC's investment decisions before TSMC sees the revenue.
What is the risk that AI efficiency improvements slow TSMC's growth?
If AI model training requires significantly less compute per unit of capability faster than the semiconductor industry is modeling - hyperscaler GPU demand could normalize sooner than current projections suggest. TSMC's $52-56 billion annual capex is sized for sustained high AI compute demand. The specific metric to watch is compute efficiency per AI benchmark: how many GPU-hours it takes to train a model of a given capability level. That metric has been improving. If it improves faster than expected, the demand assumptions behind TSMC's capacity expansion shift.
Why did the CHIPS Act mainly benefit TSMC instead of creating domestic competition?
The CHIPS Act funds domestic semiconductor manufacturing, but the company with the expertise to actually build advanced node fabs at scale in the US is TSMC. Intel Foundry is struggling technically. Samsung's US foundry presence is limited. The result is that CHIPS Act investment is largely flowing into TSMC's Arizona expansion rather than building a domestic alternative. Whether that is the right policy outcome is debatable. It is the current reality.